Maryam
Esmaeilian

I’m a digital designer. Most of my days are spent in VHDL, a simulator, and a lab bench next to an FPGA board.

I am a PhD candidate in Electronics, Electrical Engineering, Automation and Signal Processing (EEATS) at the LCIS Laboratory, Grenoble INP-Esisar, Université Grenoble Alpes. I am supervised by Dr. Romain Siragusa and co-supervised by Prof. David Hély, Dr. Louis Morge-Rollet and Dr. Ioana Vatajelu. My thesis is Development of a Wireless RF Link on FPGA and Associated Security Tools.

My core expertise is digital design: RTL in VHDL, simulation and verification with ModelSim, FPGA implementation with Vivado and Quartus, and synthesis with Design Compiler. I apply it to hardware security, from PUF authentication circuits to countermeasures against physical fault attacks.

Before the PhD, I completed a Master in Embedded Systems at Grenoble INP-Esisar and a Master in Computer Architecture Engineering at Iran University of Science and Technology, where I graduated first in my program.

entity maryam_esmaeilian is
  generic (
    FIELD    : string  := "Digital design, hardware security";
    LAB      : string  := "LCIS, Grenoble INP-Esisar";
    MSC_RANK : natural := 1   -- first in class, IUST
  );
  port (
    clk        : in  std_logic;           -- coffee
    ideas      : in  std_logic_vector(7 downto 0);
    papers     : out natural := 5;
    phd_done   : out std_logic := '0'  -- '1' in early 2027
  );
end entity maryam_esmaeilian;

1. 2026
   Design of Near-Field Antennas Based on Artix-7 FPGA M. Esmaeilian, A. Benouakta, L. Morge-Rollet, D. Hély, E.-I. Vatajelu, P. Maistri, R. Siragusa Journées Nationales Microondes (JNM), 2026Conference
2. 2025
   A PUF-Enhanced Ring Oscillator-Based Authentication System for IoT Devices M. Esmaeilian, L. Morge-Rollet, D. Hély, I. Vatajelu, R. Siragusa IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 1–6, 2025Conference
3. 2025
   On Power-Off Temperature Attacks Potential Against Security Sensors M. Esmaeilian, V. Beroulle, D. Hély Sensors, vol. 25, no. 6, 1912, 2025Journal
4. 2024
   Experimental Evaluation of RISC-V Micro-Architecture Against Fault Injection Attack M. Esmaeilian, H. Beitollahi Microprocessors and Microsystems, vol. 104, February 2024Journal
5. 2023
   Experimental Evaluation of Delay-Based Detectors Against Power-Off Attack M. Esmaeilian, A. Douadi, Z. Kazemi, V. Beroulle, A. Mirbaha, M. Fazeli, E.-I. Vatajelu, P. Maistri, G. Di Natale International Symposium on On-Line Testing and Robust System Design (IOLTS), July 2023Conference

Education

• 2024 – presentPhD in EEATSUniversité Grenoble Alpes, LCIS Laboratory, Valence, France. Thesis: Development of a Wireless RF Link on FPGA and Associated Security Tools.
• 2022 – 2023Master in Embedded Systems (IMESS)Grenoble INP-Esisar, Université Grenoble Alpes, Valence, France.
• 2019 – 2022Master of Computer Architecture EngineeringIran University of Science and Technology, Tehran. Thesis: Vulnerability Analysis of RISC-V Microarchitecture against Experimental Fault Injection Attacks.
• 2014 – 2018Bachelor of Computer Hardware EngineeringIslamic Azad University, Tehran North Branch.

Research experience

• 2023 – presentResearch EngineerGrenoble INP LCIS, Université Grenoble Alpes, with Prof. David Hély.
• 2023Research Intern: Countermeasures against Power-off Laser Fault AttacksGrenoble INP LCIS, with Prof. Vincent Beroulle and Prof. David Hély.
• 2022Research Intern: Delay-based Detectors against Power-off AttackGrenoble INP LCIS, with Prof. Vincent Beroulle, Dr. Zahra Kazemi, Dr. Mahdi Fazeli and Dr. Amir-Pasha Mirbaha.